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參數(shù)資料
| 型號(hào)： | 7P004FLA5701I15 |
| 英文描述： | MCU 20LD WITH A/D 4MHz, 0C to +70C, 20-SSOP 208mil, TUBE |
| 中文描述： | 周邊雜項(xiàng) |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大小： | 140K |
| 代理商： | 7P004FLA5701I15 |
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August 2000 Rev. 4 - ECO #13125
2
PCMCIA Flash Memory Card
FLA Series
PC Card Products
Block Diagram
Registers in Attribute Memory Space
Configuration Option Register
4000h
Register NAME
Status Reg.
4100h
4002h
Config. and Status Reg.
ADDRESS
D7
Soft Reset, active High
1 = Reset State
0 = End Reset State
D6
LevelReq (not supported)
D5-D0 Configuration index (not supported)
SRES
D6
LREQ
D4
COR
D5
Configuration Option Register: ADRS=4000h
D2
D1
D0
Write Only
-Configuration Index-
D3
Write Only
CSR
D2
Power Down; active High
1=Place all memory devices in power down mode
0=normal operation
Power On default=0
not supported
D1
D7
D6
D2
D5
D0
D4
PDwn
D3
not supported
Configuration Status Register: ADRS=4002h
D5
Represents the state of SRESET bit in COR (4000h)
1=Reset
0=Normal operation
Power On default
D5=0
D3
Represents the state of Power Down bit (D2) in CSR (4002h)
1=Power Down
D0
Reflects the card's Ready/Busy signal (pin 16) driven by
memory components Ready/Busy outputs.This bit allows software
polling of the card's Ready/Busy status.
1=Ready
SR
Read Only
Status Register: ADRS=4100h
D2
not supported
D0
not supported
D1
R/BSY
D5
SReset
D4
D7
D3
D6
PDwn
Vcc
Device (N-2)
Device 1
CSn
Device 2
CS1
CS0
Device Pair 0
Device Pair 1
Device 3
Device Pair (N/2 - 1)
RH#
DATA
BUS
Q0-Q7
I/O buffer
M Res
WH#
Vcc
DATA
BUS
D8-D15
control
4000h
Vcc
DATA
BUS
D0-D7
Device (N-1)
0000h
WL#
Card
Management
Registers
RL#
DATA
BUS
Q8-Q15
Device 0
Q0-Q7
WH#
WL#
CSn
RL#
RH#
Cn
At/Reg enable
CS0
C0
Control Logic
PCMCIA Interface
Ctrl
attrib. mem
CIS
EEPROM 2kB
WE#
OE#
CE2#
CE1#
REG#
A0
WP
SR Clr
Reg Clr
/SR
/PD
ADDRESS BUS
Control
Address
Bus
ADDRESS
BUFFER
Array
Address
Bus
A1-A25
Manuf ID Device ID
Device type
28F008SA
89H
A2H
28F008S5
89H
A6H
28F016S5
89H
AAH
28F004S5
89H
A7H
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