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參數(shù)資料
| 型號： | 80960HT |
| 廠商： | Intel Corp. |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 80960HA/HD/HT 32位高性能超標(biāo)量處理器 |
| 文件頁數(shù)： | 47/78頁 |
| 文件大?。?/td> | 835K |
| 代理商： | 80960HT |
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Advance Information Datasheet
47
80960JA/JF/JD/JT 3.3 V Microprocessor
4.7.1
AC Test Conditions and Derating Curves
The AC Specifications in
Section 4.7, “AC Specifications” are tested with the 50 pF load indicated
in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load
capacitance.
Table 24.
Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I
OL
. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
11.Worst-case T
condition occurs on I/O pins when pins transition from a floating high input to driving a
low output state. The Address/Data Bus pins encounter this condition between the last access of a read,
and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at
50 pF loads.
Figure 10.
AC Test Load
Output Pin
C
L
= 50 pF for all signals
C
L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 80960JA | EMBEDDED 32-BIT MICROPROCESSOR |
| 80960KA | EMBEDDED 32-BIT MICROPROCESSOR |
| 80960CF-30 | SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR |
| 80960JA-25 | CAP 10UF 10V 20% X7R SMD-1210 TR-7 PLATED-NI/SN |
| 80960JA-33 | EMBEDDED 32-BIT MICROPROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80960JA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| 80960JA-25 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| 80960JA-33 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| 80960JD | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR |
| 80960JD-33 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
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