參數(shù)資料
型號(hào)： 80960JF
廠商： Intel Corp.
英文描述： 3.3 V EMBEDDED 32-BIT MICROPROCESSOR
中文描述： 3.3伏嵌入式32位微處理器
文件頁(yè)數(shù)： 68/78頁(yè)
文件大?。?/td> 835K
代理商： 80960JF
80960JA/JF/JD/JT 3.3 V Microprocessor
68
Advance Information Datasheet
5.1
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET is
asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is
not ready, the processor can wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a
burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word.
The processor asserts the BLAST signal during the last Tw/Td states of an access. Once all data words
transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover.
The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state
completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the
bus enters the Ta state to transmit the new address.
Figure 43.
Bus States with Arbitration
Ti — IDLE STATE
Ta — ADDRESS STATE
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
To — ONCE STATE
READY — RDYRCV ASSERTED
NOT READY — RDYRCV NOT ASSERTED
BURST — BLAST NOT ASSERTED
NO BURST — BLAST ASSERTED
RECOVERED — RDYRCV NOT ASSERTED
NOT RECOVERED — RDYRCV ASSERTED
REQUEST PENDING — NEW TRANSACTION
NO REQUEST — NO NEW TRANSACTION
HOLD — HOLD REQUEST ASSERTED
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RESET — RESET ASSERTED
ONCE — ONCE ASSERTED
Tw/Td
Tr
Th
Ti
Ta
HOLD AND
NOT LOCKED
HOLD
RECOVERED AND
NO REQUEST AND
(NO HOLD OR
LOCKED)
RECOVERED AND
REQUEST
PENDING AND (NO
HOLD OR LOCKED)
NO REQUEST
AND NO HOLD
To
RESET
NOT
RECOVERED
RECOVERED AND
HOLD AND NOT
LOCKED
READY AND NO BURST
(READY AND BURST)
OR NOT READY
REQUEST PENDING
AND (NO HOLD OR
LOCKED)
NO REQUEST
AND (NO HOLD
OR LOCKED)
ONCE & RESET
DEASSERTION
REQUEST
PENDING AND
NO HOLD
相關(guān)PDF資料
PDF描述
80960 3.3 V EMBEDDED 32-BIT MICROPROCESSOR
80960CA-16 SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
80960CA-25 SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
80960CA-33 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
80960JD-33 EMBEDDED 32-BIT MICROPROCESSOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
80960JF-16 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
80960JF-25 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
80960JF-33 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
80960JT 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR
80960KA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
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