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參數(shù)資料
| 型號(hào)： | 82C52 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Serial Controller Interface |
| 中文描述： | CMOS串行控制器接口 |
| 文件頁(yè)數(shù)： | 2/19頁(yè) |
| 文件大小： | 255K |
| 代理商： | 82C52 |
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5-2
Block Diagram
Pin Description
SYMBOL
PIN
NO.
TYPE
ACTIVE
LEVEL
DESCRIPTION
RD
1
I
Low
READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data
output depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.
WR
2
I
Low
WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52.
Addressing and chip select action is the same as for read operations.
D0-D7
3-10
I/O
High
DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of
data, control and status information between the 82C52 and the CPU. For character formats
of less than 8 bits, the corresponding D7, D6 and D5 are considered “don't cares” for data
WRITE operations and are 0 for data READ operations. These lines are normally in a high
impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the
first serial data bit to be received or transmitted.
A0, A1
11, 12
I
High
ADDRESS INPUTS: The address lines select the various internal registers during CPU bus
operations.
IX, OX
13, 14
I/O
CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be
used as an external clock input in which case OX should be left open.
SDO
15
O
High
SERIAL DATA OUTPUT: Serial data output from the 82C52 transmitter circuitry. A Mark (1) is
a logic one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when
CTS is false, when RST is true, when the Transmitter Register is empty, or when in the Loop
Mode.
GND
16
Low
GROUND: Power supply ground connection.
CTS
17
I
Low
CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem
Status Register. Any change of state in CTS causes INTR to be set true when INTEN and
MIEN are true. A false level on CTS will inhibit transmission of data on the SD0 output and will
hold SD0 in the Mark (high) state. If CTS goes false during transmission, the current character
being transmitted will be completed. CTS does not affect Loop Mode operation.
READ/WRITE
CONTROL
LOGIC
DATA
BUS
BUFFER
PROGRAM-
MABLE
BOUD RATE
GENERATOR
CONTROL
LOGIC
3 - 10
1
2
11
12
RD
WR
A0
A1
28
CSO
14
21
OX
CO
23
24
RST
INTR
13
IX
I
TRANSMITTER
BUFFER
REGISTER
UART
CONTROL AND
STATUS
REGISTERS
RECEIVER
BUFFER
REGISTER
MODEM
CONTROL AND
STATUS
REGISTERS
18
17
19
20
DSR
CTS
DTR
RTS
TRANSMITTER
REGISTER
P
RECEIVER
REGISTER
P
S
15
25
SDO
SDI
22
26
TBRE
DR
S
D0-D7
82C52
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C52_06 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Serial Controller Interface |
| 82C53 | 制造商:UTC-IC 制造商全稱(chēng):UTC-IC 功能描述:VOLTAGE DETECTORS |
| 82C54 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:CHMOS PROGRAMMABLE INTERVAL TIMER |
| 82C54/BJA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog Timer Circuit |
| 82C54_05 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Programmable Intervel Timer |
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