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參數(shù)資料
| 型號： | 83336-00 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR 83336 PLL INTEGER-N |
| 標準包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 整數(shù) N/PLL |
| 頻率： | 3GHz |
| 適用于相關產(chǎn)品： | PE83336 |
| 已供物品： | 板 |
| 其它名稱： | 83336-0 83336-0-ND PE83336EK |
Product Specification
PE83336
Page 11 of 12
Document No. 70-0137-05 │ www.psemi.com
2010-2012 Peregrine Semiconductor Corp. All rights reserved.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency; PD_D
pulses result in a decrease in VCO frequency (for
a positive Kv VCO).
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_
U and
PD_
D waveforms, which is driven through a series
2 k
Ω resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_
U and PD_D.
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“l(fā)ow”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “l(fā)ow”. The width of either pulse is directly
proportional to phase offset between the two input
signals, fp and fc.
The phase detector gain is equal to 2.7 V / 2 π,
which numerically yields 0.43 V / radian.
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
Reserved**
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming as directed by the
Bmode and
Smode inputs.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Prescaler output
Drives the raw internal prescaler output onto the Dout output.
Bit 7
fp, fc
OE
fp, fc outputs disabled.
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 83336-00000850-01 | 制造商:Honeywell Sensing and Control 功能描述:83336-00000850-01 Vehicle Control (Hobbs) 制造商:Honeywell Sensing and Control / Hobbs 功能描述:83336-00000850-01 Vehicle Control (Hobbs) |
| 83336-21 | 制造商:Peregrine Semiconductor 功能描述:PHASE-LOCK-LOOP (PLL) |
| 83336-22 | 功能描述:IC PLL INTEGER-N 3GHZ 44CQFJ RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:UltraCMOS™ 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| 83336E 009100 | 功能描述:多芯電纜 18AWG 3C SHIELD 100ft SPOOL WHITE RoHS:否 制造商:Alpha Wire 導體數(shù)量:3 線規(guī) - 美國線規(guī)（AWG）:16 絞合:19 x 29 屏蔽:Shielded 長度:100 ft 電壓額定值:600 V 外殼材料:Polytetrafluoroethylene (PTFE) 絕緣材料:Polytetrafluoroethylene (PTFE) 類型:Communication and Control |
| 83336E 0091000 | 功能描述:多芯電纜 18AWG 3C SHIELD 1000ft SPOOL WHITE RoHS:否 制造商:Alpha Wire 導體數(shù)量:3 線規(guī) - 美國線規(guī)（AWG）:16 絞合:19 x 29 屏蔽:Shielded 長度:100 ft 電壓額定值:600 V 外殼材料:Polytetrafluoroethylene (PTFE) 絕緣材料:Polytetrafluoroethylene (PTFE) 類型:Communication and Control |
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