參數(shù)資料
型號(hào): 83905AIL
英文描述: LOW SKEW, 1:6 CRYSTAL INTERFACE-TO LVCMOS/LVTTL FANOUT BUFFER
中文描述: 低偏移,1:6晶體界面對(duì)的LVCMOS / LVTTL扇出緩沖器
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 219K
代理商: 83905AIL
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
1
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83905I is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS amily of High Performance Clock
Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive
50W series or parallel terminated transmission lines. The ef-
fective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
The ICS83905I is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew
characteristics along with the 1.8V output capabilities makes
the ICS83905I ideal for high performance, single ended appli-
cations that also require a limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
6 LVCMOS / LVTTL outputs
Outputs able to drive 12 series terminated lines
Crystal oscillator interface
Crystal input frequency range: 10MHz to 40MHz
Output skew: 80ps (maximum)
RMS phase jitter @ 25MHz, (100Hz - 1MHz):
0.26ps (typical) (V
DD
= V
DDO
= 2.5V)
Phase noise:
Offset
Noise Power
100Hz ..............-129.7 dBc/Hz
1kHz ..............-144.4 dBc/Hz
10kHz ..............-147.3 dBc/Hz
100kHz ..............-157.3 dBc/Hz
5V tolerant enable inputs
Synchronous output enables
Operating power supply modes:
Full 3.3V, 2.5V and 1.8V,
mixed 3.3V core/2.5V output operating supply,
mixed 3.3V core/1.8V output operating supply,
mixed 2.5V core/1.8V output operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant
HiPerClockS
ICS
ICS83905I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Pacakge
Top View
XTAL_OUT
ENABLE 2
GND
BCLK0
V
DD
o
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
ENABLE 1
BCLK5
V
DDO
BCLK4
GND
BCLK3
V
DD
SYNCHRONIZE
SYNCHRONIZE
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
ENABLE 1
ENABLE 2
XTAL_IN
XTAL_OUT
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