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| 型號(hào)： | 840021AKILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 125 MHz, OTHER CLOCK GENERATOR, QCC16 |
| 封裝： | 3 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220EED-2, VFQFN-16 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 767K |
| 代理商： | 840021AKILF |
ICS840021AGI REVISION C JANUARY 27, 2010
10
2010 Integrated Device Technology, Inc.
ICS840021I Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Application Schematic
Figure 4A shows a schematic example of the ICS840021I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 22pF and C2 = 33pF are recommended
for frequency accuracy. For different board layout, the C1 and C2
values may be slightly adjusted for optimizing frequency accuracy.
Figure 4A. ICS840021I Schematic Example
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of ICS840021I P.C. board layout. The
crystal X1 footprint shown in this example allows installation of either
surface mount HC49S or through-hole HC49 package. The footprints
of other components in this example are listed in the Table 7. There
should be at least one decoupling capacitor per power pin. The
decoupling capacitors should be located as close as possible to the
power pins. The layout assumes that the board has clean analog
power ground plane.
Figure 4B. ICS840021I PC Board Layout Example
Table 7. Footprint Table
NOTE: Table 7, lists component sizes shown
in this layout example.
VDD
OE
VDDA
VDD
C1
22pF
R2
10
R3
43
C5
0.1u
C4
0.1u
C2
33pF
X1
Zo = 50 Ohm
C3
10uF
Q
LVCMOS
U1
ICS840021i
VDDA
1
OE
2
XTAL_OUT
3
XTAL_IN
4
VDD
8
Q0
7
GND
6
Reserv ed
5
VDD=3.3V
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2, R3
0603
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