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參數(shù)資料
| 型號(hào)： | 8412901LA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | PLD |
| 英文描述： | OT PLD, 25 ns, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 458K |
| 代理商： | 8412901LA |
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE
IMPACT PAL CIRCUITS
SRPS021 D D2920, JUNE 1986 REVISED DECEMBER 2010
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
14
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
1.5 V
tsu
tpd
tw
VIL
VIH
5 V
VCC
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8412901XA | OT PLD, 25 ns, CQCC28 |
| 8412904KA | OT PLD, 25 ns, CDFP24 |
| 8412904LA | OT PLD, 25 ns, CDIP24 |
| 8412904XA | OT PLD, 25 ns, CQCC28 |
| 8412903LX | OT PLD, 30 ns, CDIP24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8412901LX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| 8412901XA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| 8412901XX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| 84129023A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| 84129023X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
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