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參數(shù)資料
| 型號： | 8487EIB |
| 廠商： | Intersil Corporation |
| 元件分類： | RS-485 |
| 英文描述： | 【15kV ESD Protected, 1/8 Unit Load, 5V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers |
| 中文描述： | 【15kV的ESD保護，1 / 8單位負(fù)載，5V，低功耗，高速或擺率限制，RS-485/RS-422收發(fā)器 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 527K |
| 代理商： | 8487EIB |
2
FN6051.6
Pinout
ISL8487E, ISL81487L, ISL81487E (PDIP, SOIC)
TOP VIEW
Ordering Information
PART NO.
(BRAND)
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL8487EIB*
(8487EIB)
-40 to 85
8 Ld SOIC
M8.15
ISL8487EIBZ*
(8487EIB)(Note)
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
ISL8487EIP
-40 to 85
8 Ld PDIP
E8.3
ISL81487LIB*
(81487LIB)
-40 to 85
8 Ld SOIC
M8.15
ISL81487LIBZ*
(81487LIB)(Note)
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
ISL81487LIP
-40 to 85
8 Ld PDIP
E8.3
ISL81487EIB*
(81487EIB)
-40 to 85
8 Ld SOIC
M8.15
ISL81487EIBZ*
(81487EIB)(Note)
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
ISL81487EIP
-40 to 85
8 Ld PDIP
E8.3
ISL81487EIPZ
(ISL81487EIPZ)(Note)
-40 to 85
8 Ld PDIP
(Pb-free)
E8.3
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
B/Z
A/Y
GND
D
R
Truth Tables
TRANSMITTING
INPUTS
OUTPUTS
RE
DE
DI
Z
Y
X
1
1
0
1
X
1
0
1
0
0
0
X
High-Z
High-Z
1
0
X
High-Z *
High-Z *
*Shutdown Mode for ISL8487E, ISL81487L (See Note 7)
RECEIVING
INPUTS
OUTPUT
RE
DE
A-B
RO
0
0
≥
+0.2V
1
0
0
≤
-0.2V
0
0
0
Inputs Open
1
1
0
X
High-Z *
1
1
X
High-Z
*Shutdown Mode for ISL8487E, ISL81487L (See Note 7)
Pin Descriptions
PIN
FUNCTION
RO
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
RE
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
DE
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
DI
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND
Ground connection.
A/Y
±
15kV HBM ESD Protected, RS-485/422 level, noninverting receiver input and non-inverting driver output. Pin is an input (A) if
DE = 0; pin is an output (Y) if DE = 1.
B/Z
±
15kV HBM ESD Protected, RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is
an output (Z) if DE = 1.
V
CC
System power supply input (4.5V to 5.5V).
ISL8487E, ISL81487L, ISL81487E
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