參數(shù)資料
型號(hào)： 873995AY
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 873995 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, MS-026, TQFP-48
文件頁數(shù)： 3/20頁
文件大小： 332K
代理商： 873995AY
IDT / ICS LVPECL ZERO DELAY/MULTIPLIER/DIVIDER
11
ICS873995AY REV. A SEPTEMBER 11, 2008
ICS873995
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLKx /nCLKx accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING and VOH must meet the
V
PP and VCMR input requirements. Figures 3A to 3D show interface
examples for the HiPerClockS CLKx/nCLKx input driven by the
most common driver types. The input interfaces suggested here
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in
Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
INPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
Ω resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
相關(guān)PDF資料
PDF描述
874-11-3 PANEL MOUNT, CABLE TERMINATED, SMA CONNECTOR, SOLDER, RECEPTACLE
874003DG-02T 874003 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
875-100-3 CABLE TERMINATED, MALE, SMA CONNECTOR, CRIMP, PLUG
87533-1010 160 CONTACT(S), FEMALE, STRAIGHT SINGLE PART CARD EDGE CONN, SURFACE MOUNT, SOCKET
87533-1020 160 CONTACT(S), FEMALE, STRAIGHT SINGLE PART CARD EDGE CONN, SURFACE MOUNT, SOCKET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
873995AYLF 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
873995AYLFT 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Multiplier Single 48-Pin TQFP EP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK MLTPLR SGL 48TQFP EP - Tape and Reel
873995AYT 制造商:Integrated Device Technology Inc 功能描述:873995AYT - Tape and Reel
873996AY 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Multiplier Single 48-Pin TQFP EP Tray 制造商:Integrated Device Technology Inc 功能描述:873996AY - Trays
873996AYLF 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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