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參數(shù)資料
| 型號： | 8741004AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4 40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 784K |
| 代理商： | 8741004AGLF |
ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
10
ICS8741004AG REV. AMAY 29, 2008
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS8741004
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply plane
through vias, and 0.01F bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10 resistor along with
a 10
F bypass capacitor be connected to the V
DDA pin.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
VDD
VDDA
3.3V
10
10F
.01F
V_REF
Single Ended Clock Input
VDD
CLK
nCLK
R1
1K
C1
0.1u
R2
1K
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8741004AGLFT | 功能描述:時鐘合成器/抖動清除器 LVDS/HCSL PCIe Jitter Attenuator RoHS:否 制造商:IDT 輸出端數(shù)量:2 輸出電平:LVCMOS, LVDS, LVPECL 最大輸出頻率:250 MHz 輸入電平:HCSL, LVDS, LVHSTL, LVPECL 最大輸入頻率:710 MHz 電源電壓-最大:3.465 V 電源電壓-最小:3.135 V 封裝 / 箱體:VFQFN-40 封裝: |
| 8741004AGT | 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ SYNTHESIZER SGL 24TSSOP - Tape and Reel |
| 8741004BGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS⑩ JITTER ATTENUATOR |
| 8741004BGILF | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 8741004BGILFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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