參數(shù)資料
型號(hào): 883
元件分類: 運(yùn)算放大器
英文描述: 0.1 Amp Power Operational Amplifier
中文描述: 0.1安培電源運(yùn)算放大器
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 240K
代理商: 883
ELH0041G/883/8508701ZX
0.1 Amp Power Operational Amplifier
Absolute Maximum Ratings
(T
A
e
25
§
C)
V
S
V
IN
P
D
Supply Voltage
Input Voltage (Note 1)
Power Dissipation (See curves)
Differential Input Voltage
Peak Output Current (Note 2)
Output Short Circuit
Duration (Note 3)
g
18V
g
15V
g
30V
0.5A
Continuous
T
A
Operating Temperature Range
ELH0041
Storage Temperature
Lead Temperature
(Soldering, 10 seconds)
b
55
§
C to
a
125
§
C
b
65
§
C to
a
150
§
C
T
ST
300
§
C
Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test
equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore T
J
e
T
C
e
T
A
.
Test Level
Test Procedure
100% production tested and QA sample tested per QA test plan QCX0002.
100% production tested at T
A
e
25
§
C and QA sample tested at T
A
e
25
§
C ,
T
MAX
and T
MIN
per QA test plan QCX0002.
QA sample tested per QA test plan QCX0002.
Parameter is guaranteed (but not tested) by Design and Characterization Data.
Parameter is typical value at T
A
e
25
§
C for information purposes only.
I
II
III
IV
V
DC Electrical Characteristics
V
S
e
g
15V, T
MIN
s
T
A
s
T
MAX
, C
C
e
3000 pF
Parameter
Description
Test Conditions
ELH0041
Units
Min
Typ
Max
Test
Level
V
OS
Input Offset Voltage
R
S
s
100
X
, T
A
e
25
§
C (Note 4)
1
3
I
mV
R
S
s
100
X
(Note 4)
5
I
mV
D
V
OS
/
D
T
Voltage Drift
with Temperature
R
S
s
100
X
3
V
m
V/
§
C
m
V/
0
wk
Offset Voltage Drift
with Time
T
A
e
25
§
C
5
V
D
V
OS
/
D
P
Offset Voltage
Change with
Output Power
15
V
m
V/W
Offset Voltage
Adjustment Range
20
V
mV
I
OS
Input Offset Current
T
A
e
25
§
C (Note 4)
30
100
I
nA
(Note 4)
300
I
nA
Offset Current Drift
with Temperature
0.1
1
IV
nA/
§
C
nA/
0
wk
Offset Current Drift
with Time
T
A
e
25
§
C
2
V
I
B
Input Bias
Current
T
A
e
25
§
C (Note 4)
100
300
I
nA
(Note 4)
1
I
m
A
R
IN
Input Resistance
T
A
e
25
§
C
0.3
1
I
M
X
2
T
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