參數(shù)資料
型號： 88EM8081XX-SAG2C000-T
廠商： MARVELL SEMICONDUCTOR INC
元件分類： 穩(wěn)壓器
英文描述： 2 A POWER FACTOR CONTROLLER, 120 kHz SWITCHING FREQ-MAX, PDSO8
封裝： GREEN, SOIC-8
文件頁數(shù)： 47/64頁
文件大?。?/td> 667K
代理商： 88EM8081XX-SAG2C000-T
Design and Applications Information
SW Pin to MOSFET Gate
Copyright 2010 Marvell
Doc. No. MV-S106340-01 Rev. B
August 6, 2010, Preliminary Information
Document Classification: Proprietary
Page 51
5.5
SW Pin to MOSFET Gate
The 88EM8080/88EM8081 provides a 1.2A (typical) drive current, which is the strongest driver
capability in comparison with the other similar part on the market. A gate resistor of about 20
is
used between the SW pin and the gate of the external MOSFET. The gate driver loop is subject to
fast rise and the layout trace should be kept as short as possible in order to minimize the parasitic
inductance, as shown in Figure 27.
Figure 27: SW Pin Layout Guidelines
5.6
VDD, Signal (SGND) and Power (PGND) Grounds
VDD is the IC power supply pin. It has a typical value of 12V and a maximum operating voltage of
16V. A Zener diode circuit below 16V is recommended to guarantee that the voltage on VDD will not
go any higher than 16V. The IC starts switching when VDD reaches 12V. The IC continues to switch
as long as the VDD is higher than VDD_UVLO, which is 7V (typical). An electrolytic capacitor 22μF
(typical) is recommended between VDD and ground to keep VDD above 7V during startup. After
startup, the bias transformer winding takes over and provides enough energy to power the IC. The
description of these functions can be found in Section 3.2.
A 0.01-0.1
μF ceramic capacitor is strongly recommended to be placed between the VDD and IC
ground with the layout trace as close to the IC as possible. This capacitor is used for decoupling the
noise to VDD and to maintain the VDD voltage during the switching of the internal driver circuit.
SGND is directly connected to the system ground by a Kelvin connection trace. The system ground
is the source of the MOSFET, as shown in Figure 28. PGND connects to the system ground
separately and can not share the same trace with SGND. This is due to pulse current on PGND
while driving the external MOSFET on and off. This pulse current produces pulse voltage drops on
the PGND trace and may cause the current sensing signal to be distorted if the SGND shares the
same trace. Figure 28 provides layout guidelines.
FB
Drain
OCP
VDD
Np
NS2
DR2
Rgate
VIN
ISNS
SW
SGND
Dsn
R sn
Csn
Q1
PGND
Keep this trace as short
as possible in layout
88EM8080/81
VDCin
VOUT
U3
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