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參數(shù)資料
| 型號： | 8P012SRV2203C15 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 6M X 16 MULTI DEVICE SRAM CARD, 250 ns, XMA68 |
| 封裝： | CARD-68 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 8P012SRV2203C15 |
November 2001 Rev. 1 - ECO #xxxx
4
PCMCIA SRAM Memory Card
SRV20 Series
PC Card Products
Symbol
Type
Name and Function
A0 - A25
IN PU T
A DDRESS INPUTS: A0 through A25 enable direct addressing of up
to 64MB of memory on the card. Signal A0 is not used in word access
mode. A25 is the most significant bit. (address pins used are based on
card density ,see pinout for highest used address pin)
DQ 0 - DQ 15
IN PU T/O U T
PU T
DA TA INPUT/OUTPUT: DQ 0 TH ROU GH DQ 15 constitute the
bi-directional databus. DQ 0 - DQ 7 constitute the lower (even) by te and
DQ 8 - DQ 15 the upper (odd) by te. DQ 15 is the MSB.
CE1#, CE2#
IN PU T
CA RD ENA BLE 1 A ND 2: C E1#enables even by te accesses, C E2#
enables odd by te accesses. Multiplexing A0, C E1#and C E2#allows 8-
bit hosts to access all data on DQ 0 - DQ 7.
OE#
IN PU T
OUTPUT ENA BLE: Active low signal enabling read data from the
memory card.
WE#
IN PU T
WRITE ENA BLE: Active low signal gating write data to the memory
card.
RDY/BSY#
OU TPU T
REA DY/BUSY OUTPUT: N ot used for SR AM cards
CD1#, CD2#
OU TPU T
CA RD DETEC T 1 and 2: Provide card insertion detection. These
signals are connected to ground internally on the memory card. The
host socket interface circuitry shall supply 10K-ohm or larger pull-up
resistors on these signal pins.
WP
OU TPU T
WRITE PROTECT: Follow s hardware W rite Protect Switch. W hen
Sw itch is placed in on position, signal is pulled high (10K ohm). W hen
sw itch is off signal is pulled low .
VPP1, VPP2
N .C .
PROG RA M/ERA SE POW ER SUPPLY: N ot used for SR AM
cards.
VC C
CA RD PO W ER SUPPLY: 3.3V / 5.0V for all internal circuitry .
GN D
GROUND: for all internal circuitry .
REG#
IN PU T
A TTRIBUTE MEMORY SELECT : only used with cards built with
optional attribute memory .
RST
IN PU T
RESET: N ot used for SR AM cards
WAIT#
OU TPU T
WA IT: This signal is pulled high internally for compatibility . No wait
states are generated.
BVD1, BVD2
OU TPU T
BA TTERY VOLTA G E DETEC T: Provides status of Battery
voltage.
BVD2 = BVD1 = Voh (battery voltage is guaranteed to retain data)
BVD2 = Vol, BVD1 = Voh (data is valid, battery recharge required)
BVD2 = BVD1 = Vol (data may no longer be valid, battery requires
extended recharge)
VS1, VS2
OU TPU T
VO LTA G E SENSE: N otifies the host sock et of the card's VC C
requirements. VS1 is grounded and VS2 is open to indicate a 3.3V/5V
16 bit card, w ith a 5V k ey , has been inserted.
RFU
RESERVED FO R FUTURE USE
N.C .
NO INTERNA L CONNECTION TO CA RD: pin may be driven
or left floating
Card Signal Description
SRAM
FUNCTIONAL TRUTH TABLE
READ function
Common M emory
Attribute M emory
Function Mode
/CE2 /CE1
A0
/OE
/WE
/REG
D15-D8
D7-D0
/REG
D15-D8
D7-D0
Standby Mode
H
X
High-Z
X
High-Z
Byte Access (8 bits)
H
L
H
High-Z
Even-Byte
L
High-Z
Even-Byte
HL
H
High-Z
Odd-Byte
L
High-Z
Not Valid
Word Access (16 bits)
L
X
L
H
Odd-Byte Even-Byte
L
Not Valid Even-Byte
Odd-Byte Only Access
L
H
X
L
H
Odd-Byte
High-Z
L
Not Valid
High-Z
WRITE function
Standby Mode
H
X
Byte Access (8 bits)
H
L
H
L
H
X
Even-Byte
L
X
Even-Byte
HL
H
L
H
X
Odd-Byte
L
X
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