參數(shù)資料
型號(hào): 9042RPFB
廠商: MAXWELL TECHNOLOGIES
元件分類(lèi): ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DFP28
封裝: RAD PAK, LDFP-28
文件頁(yè)數(shù): 16/26頁(yè)
文件大?。?/td> 521K
代理商: 9042RPFB
Memory
23
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
12-Bit, 41 MSPS A/D Converter
9042
08.02.02 REV 4
Power Supplies
Care should be taken when selecting a power source. Linear supplies are strongly recommended as switching sup-
plies tend to have radiated components that may be “received” by the 9042. Each of the power supply pins should be
decoupled as closely to the package as possible using 0.1 mF chip capacitors. The 9042 has separate digital and ana-
log +5 V pins. The analog supplies and the denoted AVCC digital supply pins are denoted DVCC. Although analog
and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching noise back into the analog supplies. Note that AVCC must
be held within 5% of 5 volts, however the DVCC supply may be varied according to output digital logic family (i.e.,
DVCC should be connected to the supply for the digital circuitry).
Output Loading
Care must be taken when designing the data receivers for the AD9042. It is recommended that the digital outputs
drive a series resistor of 499 ohms followed by a CMOS gate like the 74AC574. To minimize capacitive loading, there
should only be one gate on each output pin. The digital outputs of the 9042 have a unique constant slew rate output
stage. The output slew rate is about 1 V/ns independent of output loading. A typical CMOS gate combined with PCB
trace and through hole will have a load of approximately 10 pF. Therefore as each bit switches, 10 mA
of dynamic current per bit will flow in or out of the device. A full- scale transition can cause up to 120 mA (12bits 10
mA/bit) of current to flow through the digital output stage. The series resistor will minimize the output currents that can
flow in the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL
gates should be avoided since they can appreciably add to the dynamic switching currents of the 9042.
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