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參數(shù)資料
| 型號： | 908E625 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication |
| 中文描述： | 綜合四半僅符合電源橋，嵌入式微控制器和LIN串行通信 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 615K |
| 代理商： | 908E625 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
20
908E625
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SERIAL SPI INTERFACE
The SPI creates the communication link between the
microcontroller and the 908E625.
The interface consists of four terminals. See
Figure 9
:
MOSI—Master-Out Slave-In
SS
—Slave Select
MISO—Master-In Slave-Out
SPSCK—Serial Clock
A complete data transfer via the SPI consists of 2 bytes.
The master sends address and data, slave system status,
and data of the selected address.
Figure 9. SPI Protocol
During the inactive phase of
SS
, the new data transfer is
prepared. The falling edge on the
SS
line indicates the start
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
The MISO output changes data on a rising edge of
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of
SS
.
After a write operation, the transmitted data is latched into
the register by the rising edge of
SS
. Register read data is
internally latched into the SPI at the time when the parity bit
is transferred.
SS
HIGH forces MISO to high impedance.
A4:A0
Contains the address of the desired register.
R/
W
Contains information about a read or a write operation.
If R/
W
= 1, the second byte of master contains no valid
information, slave just transmits back register data.
If R/
W
= 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the
SMARTMOS
register on rising edge of
SS
.
PARITY P
The parity bit is equal to 0 if the number of 1 bits is an even
number contained within R/
W
,A4:A0. If the number of 1 bits
is odd, P equals 1. For example, if R/
W
= 1, A4:A0 = 00001,
then P equals 0.
The parity bit is only evaluated during a write operation.
BIT X
Not used.
MASTER DATA BYTE
Contains data to be written or no valid data during a read
operation.
SLAVE STATUS BYTE
Contains the contents of the System Status Register ($0c)
independent of whether it is a write or read operation or which
register was selected.
S7
S6
S5
S4
S3
S2
S1
S0
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Read/Write, Address, Parity
Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 908E625_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication |
| 908E625_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication |
| 908E626 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
| 908E626_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
| 908E626_09 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
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