參數(shù)資料
型號(hào)： 9147F-12
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 0.300 INCH, SSOP-48
文件頁數(shù)： 6/9頁
文件大小： 497K
代理商： 9147F-12
6
ICS9147-12
Electrical Characteristics at 3.3V
VDD = 3.0 3.7V, TA = 0 70
° C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Note 2: Includes VDDL = 2.5V
Note 3: VDD3 = 3.3V
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time
1
Tr1a
20pF load, 0.8 to 2.0V
CPU, 48MHz; VDD = 3.3V
-0.9
1.5
ns
Rise Time
1
Tr1b
20pF load, 0.8 to 2.0V
CPU; VDDL @ 2.5V
-1.5
2.0
ns
Fall Time
1,3
Tf1
20pF load, 2.0 to 0.8V CPU, 48MHz;
-
0.8
1.4
ns
Rise Time
1
Tr2
30pF load SDRAM 0.8 to 2.0V
-
1.0
1.6
ns
Fall Time
1
Tf2
30pF load SDRAM 2.0 to 0.8V
-
0.9
1.5
ns
Rise Time1
Tr3
30pF load PCI 0.8 to 2.0V
-
1.2
2.0
ns
Fall Time
1
Tf3
30pF load PCI 2.0 to 0.8V
-
1.1
1.9
ns
Rise Time
1,3
Tr4
20pF load, 0.8 to 2.0V
24MHz, REF (1:2) & IOAPIC
-
0.83
1.4
ns
Rise Time
1
Tr4a
45pF load, 0.8 to 2.0V , IOAPIC with
VDDL = 2.5V
-2.2
2.6
ns
Fall Time1,3
Tf4
20pF load, 2.0 to 0.8V
24MHz, REF (1:2) & IOAPIC
-
0.81
1.3
ns
Rise Time1
Tr5
Load = 45pF 0.8 to 2.0V REF0
VDD = 3.3V
1.6
2.0
ns
Fall Time
1
Tf5
Load = 45pF 2.0 to 0.8V, REF0
VDD = 3.3V
1.6
2.0
ns
Duty Cycle
1
Dt
20pF load @ VOUT=1.4V
45
50
55
%
Jitter, Cycle to Cycle
1
Tjc-c
CPU, VDDL = 3.0 to 3.7V
250
300
ps
Jitter, One Sigma
1, 2
Tj1s1
CPU; Load=20pF,
SDRAM & BUS Clocks Load = 30pF
-
50
150
ps
Jitter, Absolute
1, 2
Tjab1
CPU; Load=20pF,
SDRAM & PCI Clocks Load = 30pF
-250
-
250
ps
Jitter Absolute1
Tjab1a
PCI; Load=30pF
-500
-
500
ps
Jitter, One Sigma1
Tj1s2
REF (1:2), 48/24MHz Load=20pF,
REF0 CL = 45pF
-
1
3
%
Jitter, Absolute
1
Tjab2
REF (1:2), 48/24MHz Load=20pF,
REF0 CL = 45pF
-5
2
5
%
Input Frequency1
Fi
12.0
14.318
16.0
MHz
Logic Input Capacitance
1
CIN
Logic input pins
-
5
-
pF
Crystal Oscillator Capacitance
1
CINX
X1, X2 pins
-
18
-
pF
Power-on Time1
ton
From VDD=1.6V to 1st crossing of
66.6 MHz VDD supply ramp < 40ms
-
2.5
4.5
ms
Clock Skew
1
Tsk1
CPU to CPU; Load=20pF; @1.4V
(Same VDD)
-
150
250
ps
Clock Skew
1
Tsk2
SDRAM to SDRAM;
Load=30pF @ 1.4V
-
150
250
ps
Clock Skew
1
Tsk2
PCI to PCI; Load=20pF; @1.4V
-
300
500
ps
Clock Skew
1,2
Tsk3
CPU(20pF) to PCI (30pF); @1.4V
(CPU is early)
1
2.6
4
ns
Clock Skew
1
Tsk4
SDRAM (30pF @3.3V) to CPU
(20pF @2.5V) (2.5V CPU is late)
250
400
ps
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