參數資料
型號： 9147F-16
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁數： 4/6頁
文件大?。?/td> 415K
代理商： 9147F-16
4
ICS9147-16
Electrical Characteristics at 3.3V
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
VDDL=VDD3=3.0 3.7 V, TA = 0 70
° C unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time1
Tr1a
20pF load, 0.8 to 2.0V CPU
-
0.9
1.2
ns
Fall Time1
Tf1a
20pF load, 2.0 to 0.8V CPU
-
0.8
1.2
ns
Rise Time1
Tr1b
CL=20pF, VDD=2.5V
0.8 to 2.0V CPU
-1.0
1.2
ns
Fall Time1
Tf1b
CL=20pF, VDD=2.5V
2.0 to 0.8V CPU
-1.0
1.2
ns
Rise Time1
Tr2
30pF load, 0.8 to 2.0V
BUS & REF1
-0.9
1.6
ns
Fall Time1
Tf2
30pF load, 2.0 to 0.8V
BUS & REF1
-0.8
1.5
ns
Rise Time1
Tr3
20pF load, 0.8 to 2.0V
48 clock & REF (2:3)
-1.4
2.4
ns
Fall Time1
Tf3
20pF load, 2.0 to 0.8V
48 clock & REF (2:3)
-1.8
2.4
ns
Rise Time1
Tr4
20pF load, 0.8 to 2.0V , IOAPIC with
VDDL = 2.5V
--
1.6
ns
Fall Time1
Tf4
20pF load, 2.0 to 0.8V, IOAPIC with
VDDL = 2.5V
--
1.6
ns
Duty Cycle1
Dt1
20pF load @ VOUT=1.4V
45
50
55
%
Duty Cycle1
Dt2
REF (1:3) Load = 20pF REF 2, 3
Load = 47pF REF1
40
45
50
%
Jitter, One Sigma1
Tjis1
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
-
50
150
ps
Jitter, Absolute1
Tjab1
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
-250
-
250
ps
Jitter, One Sigma1
Tjis2
REF1; Load = 47pF
-
55
250
ps
Jitter, Absolute1
Tjab2
REF1; Load = 47pF
-500
200
500
ps
Input Frequency1
Fi
12.0
14.318
16.0
MHz
Logic Input Capacitance1
CIN
Logic input pins
-
5
-
pF
Oscillator Input Capacitance1
CINX
X1, X2 pins
-
18
-
pF
Power-on Time1
ton
From VDD=3.0V to 1st crossing of
66.6 MHz VDD supply ramp < 1 ms
-1.5
3.0
ms
Clock Skew1
Tsk1
CPU to CPU; Load=20pF; @1.4V
(Same VDD)
-
150
250
ps
Clock Skew1
Tsk2
BUS to BUS; Load=20pF; @1.4V
-
300
500
ps
Clock Skew1
Tsk3
CPU to BUS; Load=20pF; @1.4V
(CPU is early) (All at 3.3V)
13.3
4
ns
Clock Skew1
Tsk4
CPU @ 2.5V to BUS @ 3.3V
1
4
ns
Tsk5
REF @ 3.3V to IOAPIC @ 2.5V
1.5
ns
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