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參數(shù)資料
| 型號： | 91857AG-LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 91857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 164K |
| 代理商： | 91857AG-LF |
5
ICS91857
0494C—08/15/05
Recommended Operating Condition for DDR200/266/333 (see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDDQ, AVDD
2.3
2.7
V
CLKT, CLKC, FB_INC
VDDQ/2 - 0.18
V
PD#
-0.3
0.7
V
CLKT, CLKC, FB_INC
VDDQ/2 + 0.18
V
PD#
1.7
VDDQ + 0.6
V
DC input signal voltage
(note 2)
-0.3
VDDQ
V
DC - CLKT, FB_INT
0.36
VDDQ + 0.6
V
AC - CLKT, FB_INT
0.7
VDDQ + 0.6
V
Output differential cross-
voltage (note 4)
VOX
VDDQ/2 - 0.15
VDDQ/2 + 0.15
V
Input differential cross-
voltage (note 4)
VIX
VDDQ/2 - 0.2
VDDQ/2 + 0.2
V
High level output
current
IOH
0.12
mA
Low level output current
IOL
12
mA
Input slew rate
SR
14
V/ns
Operating free-air
temperature
TA
070
°C
Differential input signal
voltage (note 3)
VID
Low level input voltage
VIL
High level input voltage
VIH
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
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