參數(shù)資料
型號： 9250YF-27LF-T
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, 0.25 INCH PITCH, ROHS COMPLIANT, MO-118, TSSOP-56
文件頁數(shù)： 10/15頁
文件大?。?/td> 195K
代理商： 9250YF-27LF-T
IDTTM
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
0395F—01/25/10
ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
4
2
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Truth Table
Byte 0: Control Register
(1 = enable, 0 = disable)
t
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B#
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6
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R0
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5
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R0
)
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v
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I
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e
v
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(
4
t
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BD
I
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e
v
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e
s
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R0
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v
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I
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v
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A
(
3
t
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m
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f
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=
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1
(
1)
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v
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t
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I
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(
2
t
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B6
21
z
H
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8
41
)
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v
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A
(
1
t
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B5
20
z
H
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8
41
)
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v
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t
c
a
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I
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(
0
t
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B9
42
K
L
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U
P
C1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
t
i
B#
n
i
Pe
m
a
ND
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B6
37
M
A
R
D
S1
)
e
v
i
t
c
a
n
I
/
e
v
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t
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A
(
6
t
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B7
36
M
A
R
D
S1
)
e
v
i
t
c
a
n
I
/
e
v
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t
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A
(
5
t
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B9
35
M
A
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D
S1
)
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v
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t
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I
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e
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A
(
4
t
i
B0
44
M
A
R
D
S1
)
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v
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t
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a
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I
/
e
v
i
t
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A
(
3
t
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B2
43
M
A
R
D
S1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
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A
(
2
t
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B3
42
M
A
R
D
S1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B5
41
M
A
R
D
S1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
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B6
40
M
A
R
D
S1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
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