參數(shù)資料
型號(hào)： 92HD001XX3PRGXYYX8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 編解碼器
英文描述： PCM CODEC, PQFP48
封裝： ROHS COMPLIANT, LQFP-48
文件頁數(shù)： 53/124頁
文件大?。?/td> 1186K
代理商： 92HD001XX3PRGXYYX8
92HD001
2-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
IDT
2-CHANNEL HIGH DEFINITION AUDIO CODEC
34
92HD001
V 1.1 01/08
IDT CONFIDENTIAL
5.4.13. AFG GPIOEn
[1]
Data1
RW
0x0
Data for GPIO1 (Pin 34). If this GPIO bit is
configured as Sticky (edge-sensitive) input, it
can be cleared by writing zero (one) here when
the corresponding Polarity Control bit is zero
(one).
[0]
Data0
RW
0x0
Data for GPIO0 (Pin 33). If this GPIO bit is
configured as Sticky (edge-sensitive) input, it
can be cleared by writing zero (one) here when
the corresponding Polarity Control bit is zero
(one).
Table 34. AFG GPIOEn Command Verb Format
Verb ID
Payload
Response
Get
F16
00
See bitfield table
Set1
716
See bits [7:0] of bitfield table
0000_0000h
Table 35. AFG GPIOEn Command Response Format
Bit
Bitfield Name
RW
Reset
Description
[31.:4]
Rsvd
R
0x0
Reserved
[3]
Mask3
RW
0x0
Enable for GPIO3:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
[2]
Mask2
RW
0x0
Enable for GPIO2:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
[1]
Mask1
RW
0x0
Enable for GPIO1:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
[0]
Mask0
RW
0x0
Enable for GPIO0:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
Table 33. AFG GPIO Command Response Format
Bit
Bitfield Name
RW
Reset
Description
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