參數(shù)資料
型號(hào): 92HD001XX5PRGXYYX8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 編解碼器
英文描述: PCM CODEC, PQFP48
封裝: ROHS COMPLIANT, LQFP-48
文件頁(yè)數(shù): 32/124頁(yè)
文件大?。?/td> 1186K
代理商: 92HD001XX5PRGXYYX8
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92HD001
2-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
IDT
2-CHANNEL HIGH DEFINITION AUDIO CODEC
15
92HD001
V 1.1 01/08
IDT CONFIDENTIAL
1. With +30 dB Boost on, 1.00 Vrms with Boost off.
2. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz
bandwidth.
3. ± 1dB limits for Line Output & 0 dB gain, at -20dBV
4. Ratio of Full Scale signal to THD+N output with -3dB signal, measured “A weighted” over a 20 Hz to a 20 KHz
bandwidth. Sample Frequency = 48 KHz.
5. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz
bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
6. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency.
7. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
8. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a
bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output.
1. With +30dB Boost on, 1.00 Vrms with Boost off.
2. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz
bandwidth.
3. ± 1dB limits for Line Output & 0 dB gain, at -20dBV
4. Ratio of Full Scale signal to THD+N output with -3dB signal, measured “A weighted” over a 20 Hz to a 20 KHz
bandwidth. Sample Frequency = 48 KHz.
Any Analog Input to ADC (10 KHz Signal Frequency) Crosstalk
--85
-
dB
Any Analog Input to ADC (1 KHz Signal Frequency) Crosstalk
--80
-
dB
Spurious Tone Rejection
-
-100
-
dB
Attenuation, Gain Step Size ANALOG
-1.5
-
dB
Attenuation, Gain Step Size DIGITAL
-0.75
-
dB
Input Impedance
-50
-
K
Ω
Input Capacitance
-15
-
pF
VREFout
-
0.5 X AVdd
-
V
VREF
-
0.45X AVdd
0.5
V
Interchannel Gain Mismatch ADC
--
0.5
dB
Interchannel Gain Mismatch DAC
--
-
dB
Gain Drift
-
100
-
ppm/C
DAC Offset Voltage
-5
10
mV
Deviation from Linear Phase
-
10
1
deg.
All Analog Outputs Load Resistance
-10
-
K
Ω
All Analog Outputs Load Capacitance
-
50
pF
HEADPHONE_OUT Load Resistance
-32
-
W
HEADPHONE_OUT Load Capacitance
-100
-
pF
Mute Attenuation
--
-
dB
PLL lock time
-
96
200
μsec
PLL (or Azalia Bit CLK) 24.576 MHz clock jitter
-
100
300
psec
Parameter
Min
Typ
Max
Unit
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