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參數(shù)資料
| 型號(hào)： | 92HD83C1C5NLGXYYX8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, QCC48 |
| 封裝： | ROHS COMPLIANT, QFN-48 |
| 文件頁(yè)數(shù)： | 124/299頁(yè) |
| 文件大小： | 3779K |
| 代理商： | 92HD83C1C5NLGXYYX8 |
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21
92HD83
V 0.98 04/09
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
92HD83
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
PC AUDIO
2.9.
AFG D3
The D3-default state is available for HD Audio compliance. All converters are shut down. Port ampli-
fiers and references are active but in a low power state to prevent pops. Resume times may be
longer than those from D2, but still less than 10mS to meet Intel low power goals. The default power
state for the Audio Function Group after power is applied is D3.
The traditional use for D3 was as a transitional state before power was removed (D3 cold) before the
system entered into standby, hibernate, or shut-down. To conserve power, Intel now promotes using
D3 whenever there are no active streams or other activity that requires the part to consume full
power. The system remains in S0 during this time. When a stream request or user activity requires
the CODEC to become active, the driver will immediately transition the CODEC from D3 to D0. To
enable this use model, the CODEC must resume within 10mS and not pop. Intel HDA ECR-15b /
Low Power White paper power goals are < 30mW when analog PC_Beep is not enabled, and <
60mW when analog PC_Beep is enabled. (Charge pump and BTL amplifier power excluded.)
While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3
state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-
ior is as follows (see the ECR15b section for more information):
2.9.1.
AFG D3cold
The D3cold power state is the lowest power state available that does not use vendor specific verbs.
While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-
ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are
disabled. Per the HD Audio bus ECR 015b, the D3cold state is intended to be used just prior to
removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec
may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from
D3cold is less than 200mS.
2.10. Vendor Specific Function Group Power States D4/D5
The 92HD83 introduces vendor specific power states. A vendor defined verb is added to the Audio
Function Group that combines multiple vendor specific power control bits into logical power states
for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined
in the HD Audio specification and ECR15b. The Vendor Specific D4 state provides lower digital
power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-
ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-
log power consumption by turning off all analog circuitry except for reset circuits.
Function
HDA Bus active
HDA Bus stopped
Port Presence Detect state
change
Unsolicited Response
Wake Event1 followed by
an unsolicited response
1.The Port Presence detect circuit is currently dependent on a clock and
must be changed to generate a wake event.
GPIO state change
Unsolicited Response
Wake Event followed by an
unsolicited response
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| 92HD92B1X5NLGXYYX8 | SPECIALTY TELECOM CIRCUIT, QCC48 |
| 92HD92B1X5NLGXYYX | SPECIALTY TELECOM CIRCUIT, QCC48 |
| 92HD92B2X5NLGXYYX8 | SPECIALTY TELECOM CIRCUIT, QCC48 |
| 92HD92B2X5NLGXYYX | SPECIALTY TELECOM CIRCUIT, QCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 92HD83C1X3NLGXYBX | 制造商:Integrated Device Technology Inc 功能描述:AUD CODEC 2ADC / 3DAC 24BIT 48PIN VFQFPN - Bulk |
| 92HD83C1X3NLGXYBX8 | 制造商:Integrated Device Technology Inc 功能描述:AUD CODEC 2ADC / 3DAC 24BIT 48PIN VFQFPN - Tape and Reel |
| 92HD83C1X3NLGXYCX | 制造商:Integrated Device Technology Inc 功能描述:AUD CODEC 2ADC / 3DAC 24BIT 48PIN VFQFPN - Bulk |
| 92HD83C1X3NLGXYCX8 | 制造商:Integrated Device Technology Inc 功能描述:AUD CODEC 2ADC / 3DAC 24BIT 48PIN VFQFPN - Tape and Reel |
| 92HD83C1X5NLGXYBX | 制造商:Integrated Device Technology Inc 功能描述:92HD83C1X5NLGXYBX - Bulk |
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