參數(shù)資料
型號: 930104703
廠商: ATMEL CORP
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 30 ns, CDIP32
封裝: 0.400 INCH, CERAMIC, SIDE BRAZED, DIP-32
文件頁數(shù): 16/16頁
文件大小: 810K
代理商: 930104703
9
4151O–AERO–01/10
M65608E
Write Cycle 2
WE Controlled, OE Low
Write Cycle 3
CS1 or CS2 Controlled
Note:
The internal write time of the memory is defined by the overlap of CS1 Low and CS2 High and WE
Low. Both signals must be actived to initiate a write and either signal can terminate a write by
going inactived. The data input setup and hold timing should be referenced to the active edge of
the signal that terminates the write. Data out is high impedance if OE =
VIH.
相關PDF資料
PDF描述
930105001 8K X 16 DUAL-PORT SRAM, 30 ns, QFP84
930105002 8K X 16 DUAL-PORT SRAM, 45 ns, QFP84
930105201 512K X 8 STANDARD SRAM, 17 ns, DFP36
9301DC 93 SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, CDIP16
9301PC 93 SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDIP16
相關代理商/技術參數(shù)
參數(shù)描述
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