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參數(shù)資料
| 型號： | 930104704 |
| 廠商： | ATMEL CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 30 ns, PDFP32 |
| 封裝： | 0.400 INCH, FP-32 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 810K |
| 代理商： | 930104704 |
7
4151O–AERO–01/10
M65608E
Data Retention Mode
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and sup-
ply current are guaranteed over temperature. The following rules ensure data retention:
1. During data retention chip select CS1 must be held high within VCC to VCC -0.2V or,
chip select CS2 must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-
mizing power dissipation.
3. During power up and power-down transitions CS1 and OE must be kept between VCC +
0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V.
4. The RAM can begin operation > TR ns after VCC reaches the minimum operation volt-
ages (4.5V).
Timing
Data Retention Characteristics
Notes: 1. TAVAV = Read Cycle Time
2. CS1 =
VCC or CS2 = CS1 = GND, Vin = GND/VCC, this parameter is only tested at
VCC = 2V.
3. Parameters guaranteed but not tested
Parameter
Description
Minimum
Typical
TA = 25
C
Maximum
Unit
VCCDR
VCC for data retention
2.0
–
V
TCDR
Chip deselect to data retention time
0.0
–
ns
TR
Operation recovery time
TAVAV(1)
––
ns
ICCDR1
Data retention current at 2.0V
–0.1
150
A
ICCDR2(2)
Data retention current at 3.0V
–0.2
200
A
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| 930105002 | 8K X 16 DUAL-PORT SRAM, 45 ns, QFP84 |
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