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參數(shù)資料
| 型號： | 9324FMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5-Bit Comparator |
| 中文描述： | 93 SERIES, 5-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, CDFP16 |
| 封裝： | CERAMIC, FP-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 118K |
| 代理商： | 9324FMQB |
Switching Characteristics
V
CC
e a
5.0V, T
A
e a
25
§
C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
t
PHL
Propagation Delay
E to A
e
B
14
14
ns
t
PLH
t
PHL
Propagation Delay
A
n
, B
n
to A
l
B
25
22
ns
t
PLH
t
PHL
Propagation Delay
A
n
, B
n
to A
k
B
26
21
ns
t
PLH
t
PHL
Propagation Delay
A
n
, B
n
to A
e
B
30
32
ns
Functional Description
The ’24 5-bit comparators use combinational circuitry to di-
rectly generate ‘‘A greater than B’’ and ‘‘A less than B’’
outputs. As evident from the logic diagram, these outputs
are generated in only three gate delays. The ‘‘A equals B’’
output is generated in one additional gate delay by decoding
the ‘‘A neither less than nor greater than B’’ condition with a
NOR gate. All three outputs are activated by the active LOW
Enable Input (E).
Tying the A
l
B output from one device into an A input on
another device and the A
k
B output into the corresponding
B input permits easy expansion.
The A4 and B4 inputs are the most significant inputs and
A0, B0 the least significant. Thus if A4 is HIGH and B4 is
LOW, the A
l
B output will be HIGH regardless of all other
inputs except E.
Truth Table
Inputs
Outputs
E
A
n
B
n
A
k
B
A
l
B
A
e
B
H
L
L
L
X
X
L
L
L
H
L
L
H
L
L
H
L
L
Word A
e
Word B
Word A
l
Word B
Word B
l
Word A
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Logic Symbol
TL/F/9792–2
V
CC
e
Pin 16
GND
e
Pin 6
3
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