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參數(shù)資料
| 型號(hào)： | 933324290652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDIP14 |
| 封裝： | PLASTIC, SOT-27-1, DIP-14 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | 933324290652 |
January 1995
4
Philips Semiconductors
Product specication
Quadruple 2-input NAND Schmitt trigger
HEF4093B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
5
90
185 ns
63 ns
+ (0,55 ns/pF) CL
In → On
10
tPHL
40
80 ns
29 ns
+ (0,23 ns/pF) CL
HIGH to LOW
15
30
60 ns
22 ns
+ (0,16 ns/pF) CL
5
85
170 ns
58 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
40
80 ns
29 ns
+ (0,23 ns/pF) CL
15
30
60 ns
22 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120 ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
5
60
120 ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
1300 fi +∑(foCL) × VDD2
where
dissipation per
10
6400 fi +∑(foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
18 700 fi +∑(foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
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