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參數(shù)資料
| 型號： | 933406750652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 24-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 156K |
| 代理商： | 933406750652 |
January 1995
6
Philips Semiconductors
Product specication
24-stage frequency divider and oscillator
HEF4521B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
Output transition times
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Minimum I2 pulse
5
80
40
ns
see also waveforms
Fig.5
width; HIGH
10
tWI2H
40
20
ns
15
30
15
ns
Minimum MR
5
70
35
ns
pulse width; HIGH
10
tWMRH
40
20
ns
15
30
15
ns
Recovery time
5
20
10
ns
for MR
10
tRMR
15
5ns
15
0
ns
Maximum clock
5
6
12
MHz
pulse frequency
10
fmax
12
25
MHz
15
17
35
MHz
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
1 200 fi +∑ (foCL) × VDD2
where
dissipation per
10
5 100 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
13 050 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL
EXTRAPOLATION
FORMULA
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