參數(shù)資料
型號: 933406770653
廠商: NXP SEMICONDUCTORS
元件分類: 計數(shù)器
英文描述: 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 24-BIT UP BINARY COUNTER, PDSO16
封裝: PLASTIC, SOT-109-1, SO-16
文件頁數(shù): 5/11頁
文件大?。?/td> 156K
代理商: 933406770653
January 1995
3
Philips Semiconductors
Product specication
24-stage frequency divider and oscillator
HEF4521B
MSI
HEF4521BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4521BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4521BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
COUNT CAPACITY
OUTPUT
COUNT CAPACITY
O18
218 = 262 144
O19
219 = 524 288
O20
220 = 1 048 576
O21
221 = 2 097 152
O22
222 = 4 194 304
O23
223 = 8 388 608
O24
224 = 16 777 216
FUNCTIONAL TEST SEQUENCE
INPUTS
CONTROL
TERMINALS
OUTPUTS
REMARKS
MR
I2
O2
VSS’VDD’O18 to O24
HL
L
VDD
VSS
L
counter is in three 8-stage sections
in parallel mode; I2 and O2 are
interconnected (O2 is now input);
counter is reset by MR
LVDD
VSS
H
255 pulses are clocked into I2,O2
(the counter advances on the LOW
to HIGH transition)
LL
L
VSS
HVSS’ is connected to VSS
LH
L
VSS
H
the input I2 is made HIGH
LH
L
VSS
VDD
HVDD’ is connected to VDD;O2 is
now made oating and becomes an
output; the device is now in the
224 mode
LVSS
VDD
L
counter ripples from an all HIGH
state to an all LOW state
A test function has been included for the reduction of the
test time required to exercise all 24 counter stages. This
test function divides the counter into three 8-stage
sections by connecting VSS’toVDD and VDD’toVSS. Via
I2 (connected to O2) 255 counts are loaded into each of
the 8-stage sections in parallel. All flip-flops are now at a
HIGH state.
The counter is now returned to the normal 24-stage in
series configuration by connecting VSS’ to VSS and VDD’to
VDD. One more pulse is entered into input I2, which will
cause the counter to ripple from an all HIGH state to an all
LOW state.
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