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參數(shù)資料
| 型號： | 933507900652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDIP14 |
| 封裝： | PLASTIC, SOT-27-1, DIP-14 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 133K |
| 代理商： | 933507900652 |
January 1995
3
Philips Semiconductors
Product specication
Quadruple 2-input NAND gate
HEF4011UB
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In → On
5
60
120
ns
25 ns
+ (0,70 ns/pF) CL
HIGH to LOW
10
tPHL
25
50
ns
12 ns
+ (0,27 ns/pF) CL
15
20
40
ns
10 ns
+ (0,20 ns/pF) CL
5
35
70
ns
8 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
20
40
ns
9 ns
+ (0,23 ns/pF) CL
15
17
35
ns
9 ns
+ (0,16 ns/pF) CL
Output transition
5
75
150
ns
15 ns
+ (1,20 ns/pF) CL
times
10
tTHL
30
60
ns
6 ns
+ (0,48 ns/pF) CL
HIGH to LOW
15
20
40
ns
4 ns
+ (0,32 ns/pF) CL
5
60
110
ns
10 ns
+ (1,00 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
Input capacitance
CIN
10
pF
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
500 fi +∑ (foCL) × VDD2
where
dissipation per
10
5 000 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
25 000 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
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