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參數(shù)資料
| 型號(hào)： | 933520200112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 標(biāo)準(zhǔn)邏輯 |
| 英文描述： | SPECIALTY LOGIC CIRCUIT, CDIP28 |
| 封裝： | CERAMIC, SOT-135V, DIP-28 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 148K |
| 代理商： | 933520200112 |
January 1995
5
Philips Semiconductors
Product specication
Universal divider
HEF4751V
LSI
Fig.4 Timing diagram showing programme data inputs.
Allocation of data input
FETCH
PERIOD
INPUTS
A3
A2
A1
A0
B3 B2 B1 B0
SI
0n0A
n0B
bin
1n1A
n1B
X
2n2A
n2B
X
3n3A
n3B
X
4n4A
n4B
X
5n5A
n5B
X
6M
C0b
control
1
2
channel
control
X
Allocation of data input B3 to B0 during fetch period 6
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
B3
B2
C0b DIVISION RATIO
LL
1
LH
2
HL
5
H
10/11
B1
B0
1
2 CHANNEL CONFIGURATION
LL
H = 1
L
H
H = 2; nh =0
H
H = 2; nh =1
H
L
test state
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