參數(shù)資料
型號(hào)： 933662770129
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28
封裝： 0.600 INCH, PLASTIC, MO-015AH, SOT-117-1, DIP-28
文件頁數(shù)： 3/34頁
文件大?。?/td> 313K
代理商： 933662770129
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
11
Table 2.
Register Bit Formats
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MR1A
RxRTS
CONTROL
RxINT
SELECT
ERROR
MODE*
PARITY MODE
PARITY
TYPE
BITS PER
CHARACTER
MR1A
MR1B
0 = No
1 = Yes
0 = RxRDY
1 = FFULL
0 = Char
1 = Block
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MR2A
CHANNEL MODE
TxRTS
CONTROL
CTS
ENABLE Tx
STOP BIT LENGTH*
MR2A
MR2B
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes
0 = No
1 = Yes
0 = 0.563
4 = 0.813
8 = 1.563
C = 1.813
1 = 0.625
5 = 0.875
9 = 1.625
D = 1.875
2 = 0.688
6 = 0.938
A = 1.688
E = 1.938
3 = 0.750
7 = 1.000
B = 1.750
F = 2.000
NOTE:
*Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
CSRA
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CSRA
CSRB
RECEIVER CLOCK SELECT
TRANSMITTER CLOCK SELECT
CSRB
See Text
NOTE:
* See Table 5 for BRG Test frequencies in this data sheet, and
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CRA
CRB
MISCELLANEOUS COMMANDS
DISABLE Tx
ENABLE Tx
DISABLE Rx
ENABLE Rx
CRB
Not used –
should be 0
See Text
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE:
*Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot
be loaded.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SRA
SRB
RECEIVED
BREAK*
FRAMING
ERROR*
PARITY
ERROR*
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
SRB
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE:
* These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are discarded
when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error
reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OP7
OP6
OP5
OP4
OP3
OP2
OPCR
0 = OPR[7]
1 = TxRDYB
0 = OPR[6]
1 = TxRDYA
0 = OPR[5]
1 = RxRDY/
FFULLB
0 = OPR[4]
1 = RxRDY/
FFULLA
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1x)
11 = RxCB(1x)
00 = OPR[2]
01 = TxCA(16x)
10 = TxCA(1x)
11 = RxCA(1x)
OPR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OPR bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OP pin
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
NOTE:
The level at the OP pin is the inverse of the bit in the OPR register.
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