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參數(shù)資料
| 型號： | 933669420652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| 封裝： | SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 152K |
| 代理商： | 933669420652 |
December 1990
6
Philips Semiconductors
Product specication
Quad D-type ip-op; positive-edge trigger; 3-state
74HC/HCT173
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min. max. min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
55
20
16
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.6
tPHL
propagation delay
MR to Qn
44
16
13
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.7
tPZH/ tPZL
3-state output enable time
OEn to Qn
52
19
15
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.8
tPHZ/ tPLZ
3-state output disable time
OEn to Qn
52
19
15
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.8
tTHL/ tTLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
tW
clock pulse width
HIGH or LOW
80
16
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tW
master reset pulse
width; HIGH
80
16
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
trem
removal time
MR to CP
60
12
10
8
3
2
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
tsu
set-up time
En to CP
100
20
17
33
12
10
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.9
tsu
set-up time
Dn to CP
60
12
10
17
6
5
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.9
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