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參數(shù)資料
| 型號： | 933669460652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16 |
| 封裝： | SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 102K |
| 代理商： | 933669460652 |
December 1990
8
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max. min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
72
26
21
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.10
tPHL/ tPLH
propagation delay
CP to TC
83
30
24
255
51
43
320
64
54
395
77
65
ns
2.0
4.5
6.0
Fig.10
tPHL/ tPLH
propagation delay
CP to RC
47
17
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.11
tPHL/ tPLH
propagation delay
CE to RC
33
12
10
130
26
22
165
33
28
195
39
33
ns
2.0
4.5
6.0
Fig.11
tPHL/ tPLH
propagation delay
Dn to Qn
61
22
18
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.12
tPHL/ tPLH
propagation delay
PL to Qn
61
22
18
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.13
tPHL/ tPLH
propagation delay
U/D to TC
44
16
13
190
38
32
240
48
41
285
57
48
ns
2.0
4.5
6.0
Fig.14
tPHL/ tPLH
propagation delay
U/D to RC
50
18
14
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.14
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.15
tW
clock pulse width
HIGH or LOW
125
25
21
28
10
8
155
31
26
195
39
33
ns
2.0
4.5
6.0
Fig.10
tW
parallel load pulse width
LOW
100
20
17
22
8
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.15
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