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參數(shù)資料
| 型號(hào)： | 933669560652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16 |
| 封裝： | SOT-38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 13/15頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | 933669560652 |
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December 1990
7
Philips Semiconductors
Product specication
8-bit addressable latch
74HC/HCT259
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
D to Qn
58
21
17
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
An to Qn
58
21
17
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
LE to Qn
55
20
16
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.6
tPHL
propagation delay
MR to Qn
50
18
14
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.9
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
119
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
tW
LE pulse width
HIGH or LOW
70
14
12
17
6
5
90
18
15
105
21
18
ns
2.0
4.5
6.0
Fig.6
tW
MR pulse width
LOW
70
14
12
17
6
5
90
18
15
105
21
18
ns
2.0
4.5
6.0
Fig.9
tsu
set-up time
D, An to LE
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Figs 10 and 11
th
hold time
D to LE
0
19
6
5
0
ns
2.0
4.5
6.0
Fig.10
th
hold time
An to LE
2
11
4
3
2
ns
2.0
4.5
6.0
Fig.11
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