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| 型號(hào)： | 933669660652 |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 600 ns, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001AE, SOT-38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 7/25頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | 933669660652 |
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15
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 5-1.
Data Memory Map (Byte Addressing)
5.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU cycles as described in Figure 5-2.
Figure 5-2.
On-chip Data SRAM Access Cycles
0x0000 ... 0x003F
0x0040 ... 0x005F
0x0060 ... 0x3EFF
0x3F00 ... 0x3F01
0x3F02 ... 0x3F3F
0x3F40 ... 0x3F41
0x3F42 ... 0x3F7F
0x3F80 ... 0x3F81
0x3F82 ... 0x3FBF
0x3FC0 ... 0x3FC3
0x3FC4 ... 0x3FFF
0x4000 ... 0x41FF/0x43FF
0x4400 ... 0xFFFF
I/O SPACE
SRAM DATA MEMORY
(reserved)
NVM LOCK BITS
(reserved)
CONFIGURATION BITS
(reserved)
CALIBRATION BITS
(reserved)
DEVICE ID BITS
(reserved)
FLASH PROGRAM MEMORY
(reserved)
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
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