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參數(shù)資料
| 型號： | 933669870652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 55K |
| 代理商： | 933669870652 |
December 1990
6
Philips Semiconductors
Product specication
Quad bistable transparent latch
74HC/HCT75
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
ICC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND=0V; tr =tf = 6 ns; CL =50pF
INPUT
UNIT LOAD COEFFICIENT
nD
LEn-n
0.75
1.00
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min. max. min.
max.
tPHL/ tPLH
propagation delay
nD to nQ
15
28
35
42
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
nD to nQ
15
28
35
42
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
LEn-n to nQ
13
28
35
42
ns
4.5
Fig.8
tPHL/ tPLH
propagation delay
LEn-n to nQ
15
30
38
45
ns
4.5
Fig.8
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Figs 6 and 7
tW
enable pulse width
HIGH
16
4
20
24
ns
4.5
Fig.8
tsu
set-up time
nD to LEn-n
12
4
15
18
ns
4.5
Fig.9
th
hold time
nD to LEn-n
3
2
3
ns
4.5
Fig.9
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