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參數(shù)資料
| 型號(hào)： | 933670460112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 53K |
| 代理商： | 933670460112 |
January 1995
6
Philips Semiconductors
Product specication
1-to-64 bit variable length shift register
HEF4557B
LSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
Note
1. The set-up, hold and recovery times vary with the minimum number of bits selected. For other values as specified
one may interpolate as shown in the table (see previous page).
VDD
V
SYMBOL
MIN.
TYP.
Minimum clock
pulse width;
5
tWCPL
180
90 ns
LOW for CP0 or
10
or
60
30 ns
HIGH for CP1
15
tWCPH
40
20 ns
Minimum reset
5
150
75 ns
pulse width;
10
tWMRH
70
35 ns
HIGH
15
50
25 ns
Set-up times
see note
DA, DB, A/B → CP0,
5
360
180 ns
CP1
10
tsu
140
70 ns
L1 to L32 = LOW
15
90
45 ns
540
20 ns
L32 = HIGH
10
tsu
35
10 ns
15
30
5ns
Hold times
DA, DB, A/B → CP0,5
40
110 ns
CP1
10
thold
10
45 ns
L1 to L32 = LOW
15
0
30 ns
590
30 ns
L32 = HIGH
10
thold
60
20 ns
15
50
15 ns
Recovery times for MR
5
500
250 ns
L1 to L32 = LOW
10
tRMR
250
125 ns
15
150
75 ns
5
110
50 ns
L32 = HIGH
10
tRMR
70
30 ns
15
60
25 ns
Minimum clock
5
2,5
5 MHz
pulse frequency
10
fmax
7
14 MHz
15
10
20 MHz
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