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參數(shù)資料
| 型號(hào)： | 933670560652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 56K |
| 代理商： | 933670560652 |
September 1993
5
Philips Semiconductors
Product specication
Octal D-type ip-op with reset;
positive-edge trigger
74HC/HCT273
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
41
15
13
150
30
26
185
37
31
225
45
38
ns
2.0
4.5
6.0
Fig.6
tPHL
propagation delay
MR to Qn
44
16
14
150
30
26
185
37
31
225
45
38
ns
2.0
4.5
6.0
Fig.7
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
15
110
22
19
ns
2.0
4.5
6.0
Fig.6
tW
clock pulse width
HIGH or LOW
80
16
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tW
master reset pulse width
LOW
60
12
10
17
6
5
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
trem
removal time
MR to CP
50
10
9
6
2
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.7
tsu
set-up time
Dn to CP
60
12
10
11
4
3
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.8
th
hold time
Dn to CP
3
6
2
3
ns
2.0
4.5
6.0
Fig.8
fmax
maximum clock pulse
frequency
6.0
30
35
20.6
103
122
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6
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