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參數資料
| 型號： | 933714900118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數器 |
| 英文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOT-109, SO-16 |
| 文件頁數： | 5/7頁 |
| 文件大小： | 53K |
| 代理商： | 933714900118 |
January 1995
5
Philips Semiconductors
Product specication
1-to-64 bit variable length shift register
HEF4557B
LSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
Interpolation table (see note next page)
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP0, CP1 → O, O
5
240
480
ns
213 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
90
180
ns
79 ns
+ (0,23 ns/pF) CL
15
65
130
ns
57 ns
+ (0,16 ns/pF) CL
5
240
480
ns
213 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
90
180
ns
79 ns
+ (0,23 ns/pF) CL
15
65
130
ns
57 ns
+ (0,16 ns/pF) CL
MR
→ O
5
170
340
ns
143 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
80
160
ns
69 ns
+ (0,23 ns/pF) CL
15
60
120
ns
52 ns
+ (0,16 ns/pF) CL
MR
→ O
5
140
280
ns
113 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
70
140
ns
59 ns
+ (0,23 ns/pF) CL
15
55
110
ns
47 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
LENGTH CONTROL INPUTS
MINIMUM
NUMBER OF
BITS SELECTED
SET-UP, HOLD,
RECOVERY
TIMES
L1
L2
L4
L8
L16
L32
L
1
specied
HL
L
2
XH
L
3
X
H
L
5
six equal steps
XX
X
H
L
9
XX
X
H
L
17
X
H
33
specied
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