參數(shù)資料
型號： 933715040652
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16
封裝： SOT-109, SO-16
文件頁數(shù)： 2/14頁
文件大?。?/td> 152K
代理商： 933715040652
December 1990
10
Philips Semiconductors
Product specication
Quad D-type ip-op; positive-edge trigger;
3-state
74HC/HCT173
AC WAVEFORMS
Fig.6
Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the master reset (MR)
pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (CP) removal time.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the 3-state enable and
disable times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Fig.9 Waveforms showing the data set-up and hold
times from input (En, Dn) to clock (CP).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
相關(guān)PDF資料
PDF描述
933715040653 HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16
935189710118 HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16
933670050652 HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16
933669520652 HC/UH SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDIP16
935189560118 HCT SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDSO16
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