參數(shù)資料
型號(hào)： 933715160652
廠商： NXP SEMICONDUCTORS
元件分類： 總線收發(fā)器
英文描述： HCT SERIES, HEX 1-BIT DRIVER, INVERTED OUTPUT, PDSO16
封裝： PLASTIC, SO-16
文件頁(yè)數(shù)： 2/7頁(yè)
文件大小： 45K
代理商： 933715160652
December 1990
2
Philips Semiconductors
Product specication
Hex buffer/line driver; 3-state; inverting
74HC/HCT366
FEATURES
Inverting outputs
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT366 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT366 are hex inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (OE1, OE2).
A HIGH on OEn causes the outputs to assume a high
impedance OFF-state.
The ”366” is identical to the “365” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
nA to nY
CL = 15 pF; VCC = 5 V
10
11
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
30
pF
相關(guān)PDF資料
PDF描述
933670220652 HCT SERIES, HEX 1-BIT DRIVER, INVERTED OUTPUT, PDIP16
935190010112 HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDSO16
933757410118 HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDSO24
933757400112 HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDIP24
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