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參數(shù)資料
| 型號(hào)： | 933715220112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 封裝： | 3.90 MM, PLASITC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 933715220112 |
22
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
6.5.3
CLKPSR – Clock Prescale Register
Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written at run-time to vary the clock frequency and suit the application requirements. As the prescaler
divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The
division factors are given in Table 6-4.
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the
CLKPS bits:
1.
Write the signature for change enable of protected I/O register to register CCP
2.
Within four instruction cycles, write the desired value to CLKPS bits
At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has
a frequency higher than the maximum allowed the application software must make sure a sufficient division factor
is used. To make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler
settings.
Bit
7
6
5
4
3210
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPSR
Read/Write
R
R/W
Initial Value
0
0011
Table 6-4.
Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
00
1
00
01
2
00
10
4
00
11
8 (default)
01
00
16
01
32
01
10
64
01
11
128
10
00
256
10
01
Reserved
10
Reserved
10
11
Reserved
11
00
Reserved
11
01
Reserved
11
10
Reserved
11
Reserved
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| 935189350118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
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