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| 型號： | 933715220118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 封裝： | 3.90 MM, PLASITC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 933715220118 |
14
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
5.
Memories
This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the
program memory space and the data memory space.
5.1
In-System Re-programmable Flash Program Memory
The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash memory for program stor-
age. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny4/5/9/10 Program Counter
(PC) is 9 bits wide, thus capable of addressing the 256/512 program memory locations, starting at 0x000. “Memory
Programming” on page 106 contains a detailed description on Flash data serial downloading.
Constant tables can be allocated within the entire address space of program memory. Since program memory can
not be accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte
address 0x4000 in data memory (see Figure 5-1 on page 15). Although programs are executed starting from
address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data
memory.
Internal write operations to Flash program memory have been disabled and program memory therefore appears to
firmware as read-only. Flash memory can still be written to externally but internal write operations to the program
memory area will not be succesful.
Timing diagrams of instruction fetch and execution are presented in “Instruction Execution Timing” on page 9.
5.2
Data Memory
Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile memory lock bits, and
the Flash memory. See Figure 5-1 on page 15 for an illustration on how the ATtiny4/5/9/10 memory space is
organized.
The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address the inter-
nal data SRAM.
The non-volatile memory lock bits and all the Flash memory sections are mapped to the data memory space.
These locations appear as read-only for device firmware.
The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect
with post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing.
The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS
instructions reaches the 128 locations between 0x0040 and 0x00BF.
The indirect addressing reaches the entire data memory space. When using indirect addressing modes with auto-
matic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.
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