參數(shù)資料
型號(hào)： 933715420653
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
封裝： PLASTIC, SO-16
文件頁(yè)數(shù)： 7/7頁(yè)
文件大小： 55K
代理商： 933715420653
December 1990
7
Philips Semiconductors
Product specication
Quad bistable transparent latch
74HC/HCT75
AC WAVEFORMS
Fig.6
Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the latch enable input
(LEn-n) pulse width, the latch enable input to
outputs (nQ, nQ) propagation delays and
the output transition times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Fig.9
Waveforms showing the data set-up and
hold times for nD input to LEn-n input.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
相關(guān)PDF資料
PDF描述
935190280112 HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
933669870652 HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16
935190280118 HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
935188770112 HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
933824850005 HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, UUC
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