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參數(shù)資料
| 型號： | 933757410118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SO-24 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 131K |
| 代理商： | 933757410118 |
1998 Jul 08
9
Philips Semiconductors
Product specication
Programmable divide-by-n counter
74HC/HCT4059
DC CHARACTERISTIC FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
Note
1. From master preset mode to any other mode.
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min. typ. max. min. max.
min. max.
tPHL/ tPLH
propagation delay
CP to Q
58
200
250
300
ns
2.0
Fig.7
21
40
50
60
4.5
17
34
43
51
6.0
tPHL/ tPLH
propagation delay
LE to Q
50
175
220
265
ns
2.0
Fig.8
18
35
44
53
4.5
14
30
37
45
6.0
tTHL/ tTLH
output transition time
19
75
95
110
ns
2.0
Fig.7
7
15
19
22
4.5
6
13
16
19
6.0
tW
clock pulse width
CP
90
7
115
135
ns
2.0
Fig.7
18
6
23
27
4.5
15
5
90
23
6.0
trem
removal time
Kb, Kc to CP
75
19
95
110
ns
2.0
Fig.9; note 1
15
7
19
22
4.5
13
6
16
19
6.0
fmax
maximum clock pulse
frequency
4.2
12
3.4
2.8
MHz
2.0
Fig.7
21
36
17
14
4.5
25
43
20
17
6.0
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