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參數資料
| 型號： | 933768940602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數： | 3/10頁 |
| 文件大?。?/td> | 79K |
| 代理商： | 933768940602 |
Philips Semiconductors
Product specification
74F399
Quad 2-port register
2
2000 Jun 30
853–0028 24024
FEATURES
Select inputs from two data sources
Fully positive edge-triggered
DESCRIPTION
The 74F399 is the logical equivalent of a quad 2-input multiplexer
feeding into four edge-triggered flip-flops. A common Select input
determines which of two 4-bit words is accepted. The selected data
enters the flip-flops on the rising edge of the clock.
The 74F399 is a high speed quad 2-port register. They select 4 bits
of data from either of two sources (Ports) under control of a common
select input (S). The selected data is transferred to a 4-bit output
register synchronous with the Low-to-High transition of the Clock
input (CP). The 4-bit D-type output register is fully edge-triggered.
The Data inputs (I0n, I1n) and Select input (S) must be stable only a
setup time prior to and hold time after the Low-to-High transition of
the Clock input for predictable operation.
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F399
120MHz
22mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
16-pin plastic DIP
N74F399N
SOT38-4
16-pin plastic SO
N74F399D
SOT109-1
PIN CONFIGURATION
16
15
14
13
12
11
6
5
4
3
2
1
I0b
VCC
I1d
I1c
I0c
I0d
Qd
S
Qa
I1b
I0a
I1a
SF00951
10
7
Qb
Qc
9
8
GND
CP
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
I0a, I0b, I0c, I0d
Data inputs from source 0
1.0/1.0
20
A/0.6mA
I1a, I1b, I1c, I1d
Data inputs from source 1
1.0/1.0
20
A/0.6mA
S
Common Select input
1.0/1.0
20
A/0.6mA
CP
Clock input (active rising edge)
1.0/1.0
20
A/0.6mA
Qa, Qb, Qc, Qd
Register true outputs
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
9
1
S
CP
27
Qa
Qb
SF00952
VCC = Pin 16
GND = Pin 8
46
5
11
I1a
I0b
I1b
I0c
3
I0a
12
14
13
10
15
Qc
Qd
I1c
I0d
I1d
IEC/IEEE SYMBOL (IEEE/IEC)
SF00953
3
6
5
11
G1
1, 2D
1
9
MUX
7
C1
1, 2D
4
2
12
14
13
15
10
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