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參數(shù)資料
| 型號(hào)： | 933784240623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | F/FAST SERIES, DUAL 5-INPUT NOR GATE, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOT-108-1, MS-012AB, SO-14 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | 933784240623 |
Philips Semiconductors
Product specification
74F260
Dual 5-input NOR gate
2
1988 Nov 29
853–0048 95209
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F260
3.5ns
6mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
14-pin plastic DIP
N74F260N
SOT27-1
14-pin plastic SO
N74F260D
SOT108-1
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
D1c
D1b
D1a
D1d
Doe
D0d
D0a
D0b
Q1
D0c
D1e
Q0
SF00829
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
Dna, Dnb, Dnc, Dnd, Dne
Data inputs
1.0/1.0
20
A/0.6mA
Q0, Q1
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
Q0
Q1
5
6
VCC = Pin 14
GND = Pin 7
D0b
D0c
312
SF00830
D0d
D0a
12
D1a
D1b
910
D1c
D0e
13
8
D1d
11
4
D1e
IEC/IEEE SYMBOL
SF00831
6
5
3
12
1
2
9
10
13
8
11
4
≥ 1
LOGIC DIAGRAM
Q0
SF00832
5
1
2
3
12
13
D0a
D0b
D0c
D0d
D0e
Q1
6
8
9
10
11
4
D1a
D1b
D1c
D1d
D1e
VCC = Pin 14
GND = Pin 7
FUNCTION TABLE
INPUTS
OUTPUT
Dna
Dnb
Dnc
Dnd
Dne
Qn
H
X
L
X
H
X
L
X
H
X
L
X
H
X
L
X
H
L
H
H = High voltage level
L = Low voltage level
X = Don’t care
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