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參數(shù)資料
| 型號： | 933794660602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 93K |
| 代理商： | 933794660602 |
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
3
LOGIC SYMBOL
Q0 Q0 Q1 Q1
56
97
VCC = Pin 16
GND = Pin 8
1
4
15
13
10
14
CP0
SD0
RD0
CP1
SD1
RD1
J1
K0
212
SF00104
K1
J0
311
IEC/IEEE SYMBOL
SF00105
6
3
1
2
15
4
11
13
12
14
10
5
9
7
1J
C1
1K
R
S
2J
C2
2K
R
S
LOGIC DIAGRAM
5, 9
4, 10
2, 12
1, 13
6, 7
15, 14
3, 11
Qn
SDn
Kn
Qn
RDn
Jn
CPn
SF00106
VCC = Pin 16
GND = Pin 8
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
RD
CP
J
K
Q
OPERATING MODE
L
H
X
H
L
Asynchronous Set
H
L
X
L
H
Asynchronous Reset
L
X
H*
Undetermined *
H
↓
h
q
Toggle
H
↓
l
h
L
H
Load “0” (Reset)
H
↓
h
l
H
L
Load “1” (Set)
H
↓
l
q
Hold “no change”
H
X
Q
Hold “no change”
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
↓ = High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
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