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參數(shù)資料
| 型號： | 933795010602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | F/FAST SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 119K |
| 代理商： | 933795010602 |
Philips Semiconductors
Product specification
74F543, 74F544
Octal registered transceivers
74F543
Octal registered transceiver, non-inverting (3-State)
74F544
Octal registered transceiver, inverting 93-State)
2
1994 Dec 5
853-0874 14379
FEATURES
Combines74F245 and 74F373 type functions in one chip
8-bit octal transceiver with D-type latch
74F543 Non-inverting
74F544 Inverting
Back-to-back registers for storage
Separate controls for data flow in each direction
A outputs sink 20mA and source 3mA
B outputs sink 64mA and source 15mA
3-State outputs for bus-oriented applications
74F543 available in SSOP Type II package
DESCRIPTION
The 74F543 and 74F544 Octal Registered Transceivers contain two
sets of D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB, LEBA) and Output Enable
(OEAB, OEBA) inputs are provided for each register to permit
independent control of inputting and outputting in either direction of
data flow. While the 74F543 has non-inverting data path, the 74F544
inverts data in both directions. The A outputs are guaranteed to sink
24mA, while the B outputs are rated for 64mA.
FUNCTIONAL DESCRIPTION
The 74F543 and 74F544 contain two sets of eight D-type latches,
with separate input and controls for each set. For data flow from A to
B, for example, the A-to-B Enable (EAB) input must be Low in order
to enter data from A0 - A7 or take data from B0 - B7, as indicated in
the Function Table. With EAB Low, a Low signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent; a
subsequent Low-to-High transition for the LEAB signal puts the
A latches in the storage mode and their outputs no longer change
with the A inputs. With EAB and OEAB both Low, the 3-State
B output buffers are active and display the data present at the
outputs of the A latches. Control of data flow from B to A is similar,
but using the EBA, LEBA, and OEBA inputs.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F543
6.0ns
80mA
74F544
6.5ns
95mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
TA = 0°C to +70°C
DRAWING
NUMBER
24-pin plastic skinny DIP (300mil)
N74F543N,
N74F544N
SOT222–1
24-pin plastic SOL
N74F543D,
N74F544D
SOT137-1
24-pin plastic SSOP Type II
74F543DB
SOT340-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 - A7
Port A, 3-State inputs
3.5/1.0
70
A/0.6mA
B0 - B7
Port B, 3-State inputs
3.5/1.0
70
A/0.6mA
OEAB
A-to-B Output Enable input (Active Low)
1.0/1.0
20
A/0.6mA
74F543
OEBA
B-to-A Output Enable input (Active Low)
1.0/1.0
20
A/0.6mA
74F543
74F544
EAB
A-to-B Enable input (Active Low)
1.0/2.0
20
A/1.2mA
EBA
B-to-A Enable input (Active Low)
1.0/2.0
20
A/1.2mA
LEAB
A-to-B Latch Enable input (Active Low)
1.0/1.0
20
A/0.6mA
LEBA
B-to-A Latch Enable input (Active Low)
1.0/1.0
20
A/0.6mA
74F543
A0 - A7
Port A, 3-State outputs
150/40
3.0mA/24mA
74F543
B0 - B7
Port B, 3-State outputs
750/106.7
15mA/64mA
74F544
A0 - A7
Port A, 3-State outputs
150/40
3.0mA/24mA
74F544
B0 - B7
Port B, 3-State outputs
750/106.7
15mA/64mA
NOTE: One (1.0) FAST Unit Load is defined as: 20
A in the High State and 0.6mA in the Low state.
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